1. Field of the Invention
This invention relates to improvements in the pattern design used in the processing of integrated circuit structures on semiconductor wafers to form lines and contact openings and/or vias. More particularly, the invention comprises a process for adjusting the distribution or density of lines and contact openings and/or vias in a layer comprising a portion of an integrated circuit structure to make the distribution more uniform throughout the layer.
2. Description of the Related Art
In the formation of integrated circuit structures, active devices, such as transistors and diodes, are formed in and on a semiconductor wafer, such as a single crystal silicon wafer. Passive devices such as resistive and capacitive structures may also be formed at this level. These devices must be electrically connected together to form the desired electrical circuitry. Such electrical connection or "wiring" is conventionally referred to as "metallization" in the integrated circuit field, although at least some of the wiring may be done using electrically conductive materials other than metals such as ,for example, doped polysilicon, metal silicides, metal nitrides, etc. Such "metallization" includes the formation of contact openings (filled with electrically conductive material) extending through one or more first insulation layers down to the underlying electrodes of the devices (e.g., the source, drain, and gate electrodes of an MOS transistor). It also includes a patterned electrically conductive layer (formed by the masking and selective etching of a layer of electrically conductive material such as a metal layer) over such insulation layers which makes electrical contact with the underlying filled contact openings, or filled vias from such a first patterned layer through further insulation layers, and subsequent patterned layers of electrically conductive material in electrical contact with such filled vias, to thereby provide vertical electrical connections between such patterned layers of electrically conductive material.
After the initial contact openings are formed through one or more insulation layers down to the active devices, and (at least in some instances) after the filling of such contact openings with electrically conductive materials such as, for example, one or more metals, doped polysilicon, metal silicides, metal nitride, etc., a thin layer of electrically conductive material, typically a metal, is deposited over the structure by sputtering, CVD techniques, or vacuum evaporation over the entire wafer. The unwanted portions of this layer are then removed by patterning, i.e., photomasking and etch procedures, leaving the surface of the insulation layer or layers covered with thin lines of conductor. Typically one or more intermediate insulation layers are formed over this first patterned layer of electrically conductive material, and at least one subsequent patterned metal layer is then formed over such an intermediate insulation layer of layers, with metal-filled openings or vias then formed through such intermediate insulation layer or layers to provide electrical interconnection vertical between the respective patterned layer of electrically conductive material.
Thus, in the formation of lines, and contact openings and/or vias, on an integrated circuit structure both the photomasking and etching procedures which constitute the overall patterning of the lines, contact openings, and vias are important. Patterning errors can cause warped or misaligned patterns that ultimately can result in undesirable electrical characteristics. Hence, the patterning process is critical to ensuring a satisfactory product. Alignment and exposure continue to be at the heart of the photomasking portion of patterning.
During the photomasking process, an optical phenomena, diffraction, occurs which causes printing to vary from one section of the circuit to another. Diffraction is due to the bending of a wave of energy as it passes the opaque edge of a mask. Improvement of aligners has been achieved by using shorter wavelengths which lessen the diffraction effect. However, undesirable resolution and registration still occur even with shorter wavelengths.
For example, if a circuit is core limited, i.e., having lots of gates connected with metal lines, then the printing of lines in the circuit remains homogeneous. However, if the circuit has one section which is heavily populated with lines and another section which is less heavily populated with lines (hereinafter called lonely lines), then the width of the lines and the roughness of the edges of the lines vary from one section to another because of this diffraction phenomenon. As circuits become smaller, the undesirability of varying line size dramatically increases. For example, the difference in line size in one (1.0) micron technology is probably about 0.05 microns which is approximately a 5 percent difference in size. But at one-half micron (0.5) technology, the approximate size of the effect is still the same, but the difference is now approximating 10 percent, which is unacceptable.
Optical alignment and resolution can also be affected by a lack of planarity of the photoresist layer onto which the mask image is being optically projected by radiation. Various planarization techniques have been proposed, including chemical/mechanical polishing (CMP) procedures. However, such procedures, which involve the simultaneous chemical etching and mechanical abrading of several materials (e.g., metals, oxides, and organic resist materials, etc.), a non-homogeneous density of lines on an integrated circuit structure can affect the ability of such CMP procedures to produce the desired planarization of the structure.
Etching in semiconductor processing may also entail inherent limitations due to a circuit's physical layout. An ideal anisotropic etch leaves vertical walls in the resist and metal layers. However, because the etching chemical dissolves the top of the wall for a longer time than the bottom, the resulting hole is wider at the top than at the bottom. Hence the etch is isotropic. This etch undesirably undercuts the metal layer beneath the resist which may result in resist lifting or narrow lines. Dry etching processes, such as reactive ion etching, have decreased undercutting, but have not completely solved this problem.
Dry etch techniques rely in part on material from the masking layer (usually photoresist) to achieve anisotropic profiles. This has the undesirable side effect of making the etch anisotropically sensitive to masking pattern density. Hence, lonely lines in an isolated pattern will etch more isotropic than a heavily populated pattern (since less photoresist is present in areas having lonely lines). Both patterns may exist on the same chip design.
Another problem to be addressed, effectively the mirror image of the problem above, is the issue of microloading where the etching rate of the material is dependent upon the amount of material to be etched. Hence, more surface to be exposed (more materials to be removed) will take a longer period of time to etch. It logically follows that a part of a chip having different and more densely populated area lines (and therefore less material to be etched away) will take a shorter time to etch than an area of less density populated lines.
Similar problems can occur in the etching of vias and/or contact openings through insulation layers when the density of the vias and/or contact openings is not uniform across the semiconductor wafer.
Parent U.S. patent application Ser. Nos. 07/732,843 and 08/362,839, the disclosures of which are hereby incorporated by reference, address the problem of irregular line spacing or density by providing for the addition of lines referred to as "dummy lines" in areas where "lonely lines" are located.
Another factor to consider during patterning is electromigration. Typically, in circuit layout design, lines are designed to be at one predetermined width, irrespective of their future use. This layout design may create electromigration problems, especially in lines which must carry a heavy load. Long, very thin metal lines, typically formed of aluminum, carrying high currents are particularly prone to electromigration. The high current sets up an electric field in the lead and generates heat. As current and frequency increase, the electromigration resistance goes down. During the electromigration, the aluminum in the lead becomes mobile and begins to diffuse to either end of the lead. Under extreme conditions, the lead itself is severed. In the past, a worst case current density was assumed and all metal lines were made wide enough to carry that current. This is undesirable as line widths become smaller and more functions are put on a single chip.
Another phenomena occurring during patterning is inherent stress due to layering. Because various layers of material are printed on the circuit, all of which may have different coefficients of expansion/contraction and degrees of hardness, an intrinsic stress builds up between these layers. This stress may result in the linear expansion of the softer materials, i.e., generally metals, causing metal voiding even with no voltage. Therefore, stress due to layering may also produce an electrical disconnection. Such stress can also result in the expansion of the underlying metal layer, such as aluminum, into the vias in an insulation layer over the aluminum layer. When the density of the vias over such a stressed aluminum layer is not homogeneous, the amount of expansion into the less densely spaced vias can be more pronounced, sometime resulting in a volcano-like vertical expansion of the aluminum into and through such vias.
Therefore, there is need for improving the patterning design used in the processing of integrated circuit structures.